OpenPOWER Summit Europe 2019: Full Schedule

Georg Greve is a software developer, physicist, entrepreneur and co-founder of Vereign® AG. Previously he was founding president at Kolab Systems AG and the Free Software Foundation Europe (FSFE), where he received the German Federal Cross of Merit on Ribbon for his groundbreaking... Read More →

Final Georg Greve pdf

Thursday October 31, 2019 09:10 - 09:35 CET
Tete d'Or AB

Keynote Sessions

Session Slides Included Yes

09:35 CET

Keynote: OpenPOWER & Open ISA - Mendy Furmanek, Director, OpenPOWER Processor Enablement, IBM & President, OpenPOWER Foundation

Mendy is the President of the OpenPOWER Foundation and Director - OpenPOWER Processor Enablement at IBM. In her keynote, she'll provide an update on the opening up of the POWER ISA and how IBM and the Foundation are engaging with the broader open hardware ecosystem.

Speakers

Mendy Furmanek

Director, OpenPOWER Processor Enablement, IBM

Mendy Furmanek is the IBM Director, POWER Open Hardware Business Development, where she drives IBM partnerships in chip development as well as OpenCAPI partner enablement. Mendy received a BSEE with a double major in Electrical/Computer Engineering and Computer Science from Duke University... Read More →

Final Mendy F. pdf

Thursday October 31, 2019 09:35 - 10:00 CET
Tete d'Or AB

Keynote Sessions

Session Slides Included Yes

10:00 CET

Morning Break

Thursday October 31, 2019 10:00 - 10:30 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

10:30 CET

The Fletcher Framework: Accelerating Big Data Analytics on FPGAs - Zaid Al-Ars, Delft University of Technology

Modern big data systems are highly heterogeneous. Components are implemented in a wide variety of programming languages and frameworks. Due to implementation differences, interfaces between components are burdened by serialization overhead. The Apache Arrow project helps to overcome this burden through a language-agnostic columnar in-memory format for big data applications. It is currently being integrated in many big data analytics frameworks, such as Apache Spark & Parquet, Dask, Pandas, and others.
In this talk, we present the open-source Fletcher framework, which is an implementation of Arrow for FPGA accelerators. Through a design generation step, Fletcher takes Arrow data structures and generates specialized, high-performance and easy-to-use hardware interfaces that can connect to accelerator kernels. This allows for automating the design of data interfacing and management. In addition, using Arrow datatypes prevents serialization overhead, and provides out-of-the-box integration with over 11 high-level languages efficiently.

Speakers

Zaid Al-Ars

Associate Professor - Quantum & Computing Engineering Dept., TU Delft

Zaid Al-Ars an associate professor at the Quantum and Computer Engineering Department of the Delft University of Technology, where he leads the Accelerated Big Data Systems group. His work focuses on developing computing infrastructures for efficient processing of big data applications... Read More →

Thursday October 31, 2019 10:30 - 10:50 CET
Lumiere (Track 3)

FPGA

10:30 CET

POWER Functional Simulator: Jump on the Bandwagon of Open POWER ISA - Saif Abrar, IBM

As we open-source the POWER ISA, it's a golden time to spread the word about the publicly available POWER Functional Simulator.
This presentation will introduce the Functional Simulator, its capabilities and value to the users.
By implementing the behavior of all core units, and simulation of the memory, network, and system console, the Functional Simulator executes the entire software stack including loading, booting and running a LE Linux environment on a local x86 host. TCL interface allows the users to customize system initialization and processor state control.
Features available in the simulator:
- Full instruction set simulator for Power ISA
- Models complex SMP effects
- Functional behavior of units (Load/Store, FXU, FPU, VMX, VSX, etc.)
- Exceptions and Interrupt handling
- Address translation, both HPT and Radix
- Memory, SLBs, TLBs, ERATs
- Register and Memory R/W interaction

Speakers

Saif Abrar

Systems Advisory Engineer, IBM

Dr. Saif Abrar is a researcher, developer and technical-lead of the IBM Cognitive Systems simulation team in India. He earned his PhD from the Technical University of Tallinn (Estonia), after completing bachelors and masters from Aligarh Muslim University and IIT-Delhi, respectively... Read More →

PowerFuncSim OpenPowerEU pdf

Thursday October 31, 2019 10:30 - 11:10 CET
Tete d'Or CD (Track 2)

CPUs Simulation Open Hardware

Session Slides Included Yes

10:30 CET

Desktop on OpenPOWER system? YES! - Daniel Horák, Red Hat

Dog-fooding, openness, privacy. There are various reasons why to use an OpenPOWER system as a daily desktop/workstation. Thanks to the OpenPOWER ecosystem we have the hardware now, thanks to the distributions like Fedora we have the operating system and applications. What works and what doesn't, what have we fixed or what are the challenges where a help from the OpenPOWER community would be welcome.

Speakers

Daniel Horák

Principal Software Engineer, Red Hat

Long-time engineer at Red Hat taking care of Fedora for POWER and IBM z platforms.

op eu 2019 desktop openpower pdf

Thursday October 31, 2019 10:30 - 11:10 CET
Tete d'Or AB (Track 1)

OpenPOWER Ecosystem

Session Slides Included Yes

10:50 CET

Searching Through Snappy Compressed Wikipedia Articles Using Fletcher - Matthijs Brobbel, Delft University of Technology

The Accelerated Big Data Systems group at Delft University of Technology is building open source tools and solutions to enable development and effortless integration of domain-specific hardware accelerators for big data analytics in data centers. This talk demonstrates how we used these open source tools to turn an accelerator idea into an integrated demo, running on hardware in less than a week. The demo application uses the Fletcher framework to search through Snappy compressed Wikipedia articles stored in Apache Arrow buffers.

Speakers

Matthijs Brobbel

Research Engineer, Delft University of Technology

Matthijs Brobbel is a research engineer in the Accelerated Big Data Systems group at Delft University of Technology.

Thursday October 31, 2019 10:50 - 11:10 CET
Lumiere (Track 3)

FPGA

11:20 CET

Accelerating Deep Learning Inference with (Open)CAPI and Posit Numbers - Louis Ledoux, BSC (Barcelona Supercomputing Center)

In order to tackle the communication-bound problems in heterogeneous systems, this presentation will show
how intrinsic arithmetics can have significant impacts on energy and throughputs.

It will be shown that thanks to the denser representation offered by the posit arithmetic we can:
- significantly divide bandwidth needed (PCIE: HOST <-> FPGA)
- maintain all weights on chip
- saving power consumption

Speakers

Louis Ledoux

PhD candidate, BSC (Barcelona Supercomputing Center)

Louis is a PhD candidate at the Barcelona Supercomputing Center, he is currently working on arithmetics for AI algorithms at the hardware level by designing accelerators. He earned his master degree and engineer diploma at ESIR (Ecole Supérieure d'Ingénieurs de Rennes) located in... Read More →

presentation louis ledoux posit pdf

Thursday October 31, 2019 11:20 - 11:40 CET
Lumiere (Track 3)

OpenCAPI FPGA

Session Slides Included Yes

11:20 CET

microwatt: Make your own POWER CPU - Michael Neuling & Anton Blanchard, IBM

At the OpenPOWER summit USA in August, IBM presented microwatt, a reference implementation of the POWER OpenISA.

This talk will be a walk through of the microwatt design and present some of the future directions we'd love to see the project taken.

Speakers

Anton Blanchard

Distinguished Engineer, IBM

Anton has been involved with Linux and Open Source Software for over 20 years, much of that time with IBM. He leads a worldwide team dedicated to using Open Source technologies to build better products. In mid 2019he got the Open Hardware bug as a result of IBM's opening up of the... Read More →

Michael Neuling

POWER Linux enablement, IBM

Michael is a proud part of the IBM OzLabs Canberra crew where he works on IBM POWER processors. He's spent the last decade in the trenches doing bringup and enablement of new chips. He ported micropython to the initial microwatt implementation.

OPS EU 2019 microwatt pdf

Thursday October 31, 2019 11:20 - 12:00 CET
Tete d'Or CD (Track 2)

CPUs Simulation Open Hardware

Session Slides Included Yes

11:20 CET

Secure, Scalable and On Demand: AC922 VMs in IBMs Virtual Private Cloud - Carl Pecinovsky, IBM

IBM is poised to release AC922's in IBM Next Generation Cloud featuring 100Gbps network interconnects, Multiple Zone Regions, Virtual Private Cloud and a whole new set of APIs to help manage it all. Early performance testing is indicating GPU performance will blow the doors off the competition! Come to this session to get a sneak peek at this new offering - and get signed up for the no-charge Beta program while you are there!

Speakers

Carl Pecinovsky

Software Engineer, IBM

Carl Pecinovsky has worked at IBM as a software engineer for over 20 years; mostly on the POWER platform. He spent 6 years helping develop Power Virtualization Center (PowerVC) on OpenStack technologies for private cloud enterprise customers before transitioning to accelerating OpenPOWER... Read More →

Accelerated POWER in the Cloud OpenPOWERSummit October2019 pptx

Thursday October 31, 2019 11:20 - 12:00 CET
Tete d'Or AB (Track 1)

GPU Software Development

Session Slides Included Yes

11:40 CET

Near-Memory Transprecision Accelerators using CAPI/OpenCAPI and SNAP -Dionysios Diamantopoulos, IBM Research - Zurich

Approximate computing has been recognized as an effective set of techniques to overcome the energy scaling barrier of computer systems. Such techniques rely on different layers of the computing stack to exploit the intrinsic error resilience of algorithms in many application domains such as signal processing, multimedia, data analytics and machine learning. Indeed, fully accurate arithmetic in specific phases of a computation in those applications may have only a marginal effect on output quality, especially if combined with system-level design. Inspired by approximate computing, recently, transprecision computing has emerged as a computing paradigm that combines all the layers from the application to the specifically tuned hardware that supports a variety of precision settings, respective computations and configurations to access the memory. In this talk we will discuss how CAPI/OpenCAPI technology enables the transprecision computing paradigm, by allowing designers to bring-up low-precision accelerators near to the memory. In addition, the energy efficiency results of the development of such near-memory transprecision accelerators, from two application domains, i.e. scientific computing and machine learning, using a two-socket Witherspoon-POWER9 with AD9V3 FPGAs and Nvidia V100 GPUs, will be presented.

Speakers

Dionysios Diamantopoulos

Researcher, IBM Research - Zurich

Dionysios Diamantopoulos is a Post-Doc Researcher at Heterogeneous Cognitive Computing Systems Group, IBM Research - Zurich. His research interests include energy-efficient FPGA accelerators, transprecision computing and near-memory computing. He holds a PhD in computer science from... Read More →

Thursday October 31, 2019 11:40 - 12:00 CET
Lumiere (Track 3)

FPGA

12:00 CET

Lunch (Provided for OpenPower Attendees)

Thursday October 31, 2019 12:00 - 13:00 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

13:00 CET

Processing-In-Memory and Power9 - Alexandre Ghiti, Upmem

The memory bottleneck and the dominant energy cost between server processors and memory can be addressed by putting computing capability into the DRAM itself.
UPMEM designed and implemented the first Processing In Memory (PIM) architecture and 32-bit processor suitable for scalable, efficient, programmable DRAM integration. UPMEM realized a 4Gb DRAM circuit comprising 8 instances of this processor, on an unchanged DRAM process. These circuits are assembled onto standard DIMM memory modules, enabling harmless integration into standard servers. In a server, thousands of C programmable GP processors with unprecedented data bandwidth are available to data-intensive applications.

We will present the technology in details and talk about the modifications we have done in the OpenPower firmware to be able to use our DIMM on an off-the-shelf Power9 hardware.

Speakers

Alexandre Ghiti

System software engineer, Upmem

2018-2019: Upmem 2018-2019: Ensimag teacher 2014-2018: Kalray

Thursday October 31, 2019 13:00 - 13:40 CET
Tete d'Or CD (Track 2)

CPUs Accelerators

13:00 CET

Free your Database on POWER - Robert Treat, Credativ GmbH

The OpenPOWER platform is an interesting operational basis for mission critical PostgreSQL installations. With the broad adoption of Linux in the ppc64le ecosphere with the support of Little Endian distributions like Debian or Ubuntu nowadays, this opens the door for the whole PostgreSQL world gaping wide. This talk will share experiences in packaging, scaling and operating PostgreSQL on Linux on POWER and gives an overview of the currently available options.

Speakers

Robert Treat

President, credativ

Working on database-backed, internet-based systems for over a decade, Robert is a long-time user, developer, and advocate for open source technologies. Best known for his work in the Postgres community, he has contributed to numerous industry groups and organizing committees. An international... Read More →

postgres open power summit 2019 pdf

Thursday October 31, 2019 13:00 - 13:40 CET
Tete d'Or AB (Track 1)

Databases

Session Slides Included Yes

13:00 CET

Specialized Hardware Solutions for In-Database Analytics Enhanced by OpenCAPI+HBM - Kaan Kara, Systems Group, ETH Zurich

Driven by the increasing complexity of data processing tasks, specialized hardware solutions are emerging as a way to increase performance and efficiency for both relational data processing and advanced analytics such as machine learning. Recently increased usage of FPGAs as a target deployment platform in the datacenter opens up new opportunities in specializing hardware and rethinking the system architecture.

In the first part of this talk, we present an overview of our previous efforts in this domain, focusing on doppioDB: A branch of MonetDB with FPGA-based data processing capabilities. We introduce the hardware-software layer built to transparently use FPGA resources in a multi-tenant system, followed by an overview of already implemented FPGA-based operators, their advantages, and limitations.
In the second part, we shift our focus to recently available OpenCAPI-attached FPGA platforms with high-bandwidth-memory (HBM). We discuss some preliminary results on how OpenCAPI and HBM can be utilized to improve FPGA-based processing within doppioDB.

Speakers

Kaan Kara

PhD Student, Systems Group, ETH Zurich

Kaan Kara is a final year PhD student at Systems Group, ETH Zurich. His research is focused on exploring specialized hardware solutions for data analytics and machine learning, and the systems integration aspect of these solutions. He was awarded a DAAD scholarship for his Bachelor's... Read More →

Talk pdf

Thursday October 31, 2019 13:00 - 13:40 CET
Lumiere (Track 3)

OpenCAPI

Session Slides Included Yes

13:50 CET

Improving Accessibility of FPGA Accelerators using Dataflow Abstractions - Lukas Wentzel, Hasso Plattner Institute

Their flexibility to define efficient, application-specific microarchitectures and superior power efficiency make FPGA accelerators a promising platform. Nevertheless, they are only reluctantly targeted by application developers. We believe that a lack of convenient and portable runtime environments is a major factor inhibiting the widespread adoption of FPGA accelerators. Besides requiring varying degrees of hardware design expertise, application developers are presented with vendor-specific and far more complex workflows compared to software development. Furthermore, many basic facilities like resource abstractions and communication primitives, which would be provided by lower software layers like an operating system, must be custom-built into the FPGA design.

With the DataFlow ACCelerator TOolkit, we focus on these two shortcomings in order to create a flexible and lightweight environment to build FPGA designs according to the dataflow model. Building upon the CAPI SNAP framework, DFACCTO introduces a vendor-independent method of specifying a hardware design on a structural level with a high degree of abstraction. As a Python-based DSL translating to synthesizable VHDL, this method is compatible with a wide variety of targets and toolchains, despite being designed in the context of CAPI SNAP and Xilinx Vivado. Furthermore, DFACCTO defines a set of reusable components compatible with the industry-standard AMBA interconnect architecture. These components provide modular, data stream centric facilities. Thus DFACCTO enables developers to avoid reinventing common functionality in dataflow designs, without being bound to vendor-specific IP blocks.

In our talk, we will introduce the DFACCTO framework by means of an example design workflow of building a database operator. As DFACCTO is designed for extensibility, we will also discuss several points where modifications and customizations for specific use cases are possible.

Speakers

Lukas Wentzel

Researcher, Hasso Plattner Institute

In 2019, Lukas Wenzel obtained his M.Sc. in IT Systems Engineering from the Hasso Plattner Institute at the University of Potsdam, Germany.He conducted his master’s thesis in cooperation with the IBM Lab in Böblingen. There he developed the DFACCTO framework aspiring to make the... Read More →

Thursday October 31, 2019 13:50 - 14:30 CET
Lumiere (Track 3)

FPGA

13:50 CET

Porting a Distribution to Power - Observations and Achieving x86 Parity - Daniel Kolesa

The Power architecture ecosystem is in a much better shape nowadays than it used to be in the past. However, what if one were to port a distribution to it from scratch? Since the beginning of this year, I've been involved with the Void Linux distribution, doing just that, and achieved near parity with x86_64 in the meantime.

In this talk I will cover the efforts needed for initial bootstrap as well as various hurdles I've come across on the way, including toolchains for popular languages (Rust, Java, Go...), common desktop software (web browsers...), ABI and libc related problems (ELFv2...), little endian vs big endian, cross compiling and so on.

And most importantly, utilizing this work to evangelize the platform both to users and software upstreams, in order to improve and expand the OpenPOWER/Power architecture ecosystem further.

No distro knowledge is necessary for this talk.

Speakers

Daniel Kolesa

Software Engineer

I've been working with open source for as long as I can remember, on projects in various areas, including game development, programming language toolchains, GUI toolkits and multimedia. Since 2014 I've been working for the Samsung Open Source Group. My long-time projects include the... Read More →

Thursday October 31, 2019 13:50 - 14:30 CET
Tete d'Or AB (Track 1)

Linux Software Development OpenPOWER Ecosystem

13:50 CET

A Deep Dive into OpenPOWER Host OS Secure Boot - Nayna Jain, IBM

OpenPOWER host OS secure boot provides an open, flexible and secure signature verification and key management model. The keys are managed and controlled by the firmware and are used by a Linux based boot-loader to further verify the host operating system(Linux). The main features of this model are:

- A verification mechanism based on Linux kernel integrity management(IMA) subsystem.
- A pluggable architecture to support different key hierarchies and update mechanisms based on vendors’ choice.
- A pluggable storage module to handle different secure storage.

This talk discusses the end-to-end solution of OpenPOWER host OS secure boot from firmware to host operating system. The firmware and kernel patches, which also includes their interfaces and userspace, are being actively reviewed by the community.

Speakers

Nayna Jain

Software Engineer, IBM

Nayna Jain is a software designer and developer at IBM Linux Technology Center. She is involved into the secure and trusted boot development in IBM for OpenPOWER. Her experience is in the Linux Kernel security subsystem, secure boot, trusted computing, and security advocacy. She had... Read More →

Thursday October 31, 2019 13:50 - 14:30 CET
Tete d'Or CD (Track 2)

Systems Security

14:40 CET

BoF Session: OpenPOWER ISA - Anton Blanchard; Michael Neuling & Mendy Furmanek, IBM

Speakers

Mendy Furmanek

Director, OpenPOWER Processor Enablement, IBM

Anton Blanchard

Distinguished Engineer, IBM

Michael Neuling

POWER Linux enablement, IBM

Thursday October 31, 2019 14:40 - 15:20 CET
Tete d'Or AB (Track 1)

CPUs Open Hardware

14:40 CET

OpenCAPI Acceleration Framework: Unleash the Power of Customized Accelerators - Yong Lu & Alexandre Castellane, IBM

OpenCAPI Acceleration Framework, abbreviated as OC-Accel, is a platform to enable programmers and computer engineers to quickly create FPGA-based accelerations. The acceleration action's software part and hardware part share the server host memory data through OpenCAPI interface. With it, people can quickly design an accelerator and benefit from the bandwidth, latency, coherency and programability advantages of OpenCAPI.

Speakers

Alexandre Castellane

Senior Specialist Engineer, IBM France

Alexandre Castellane is a Sr specialist engineer at IBM, France. He received a Master's degree in electronics engineering from the French engineering school ENSERG in 1992. After a long carrier in analog radio test and development for 2G/3G applications, He came to high speed digital... Read More →

Yong Lu

OpenCAPI Acceleration Architect, IBM

Yong Lu is a hardware engineer in IBM Systems group. She leads the development of OpenCAPI acceleration framework, which is a platform to enable programmers and computer engineers to quickly create FPGA-based accelerations. She also actively creates and incubates CAPI/OpenCAPI based... Read More →

OpenCAPI Acceleration Framework YongLu ver2 pdf

Thursday October 31, 2019 14:40 - 15:20 CET
Lumiere (Track 3)

OpenCAPI FPGA

Session Slides Included Yes

14:40 CET

An OpenBMC Update - Gunnar Mills, IBM

OpenBMC is an open-source Baseboard Management Controller (BMC) firmware stack. Many OpenPOWER systems use OpenBMC. In March 2018 the OpenBMC project became a Linux Foundation project. This talk is an update of the OpenBMC project since becoming a Linux Foundation project. This talk will cover the formation of the technical steering committee to guide the project, the move to a standard OpenBMC release process, the growth of the project, and an update of new OpenBMC features including Redfish, PLDM, the improved web interface, and Kernel updates.

Speakers

Gunnar Mills

Software Engineer working on the OpenBMC project, IBM

Gunnar is a Software Engineer at IBM working on the OpenBMC Project. He is maintainer of 4 OpenBMC repositories, including the Web Interface, and the IBM lead for the Redfish on OpenBMC deliverable.

OP EU SUMMIT 2019 OpenBMC Update pdf

Thursday October 31, 2019 14:40 - 15:20 CET
Tete d'Or CD (Track 2)

Systems Software Development

Session Slides Included Yes

15:20 CET

Afternoon Break

Thursday October 31, 2019 15:20 - 15:50 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

15:50 CET

AI Inference Acceleration with components all in Open Hardware: OpenCAPI and NVDLA - Peng Fei Gou, IBM

NVDLA is a deep learning accelerator with both hardware and software available in open source community. IBM announced open hardware strategy recently, which focuses on building open ecosystem of OpenCAPI based heterogeneous computing system. To align with this open strategy, we proposed the solution to connect NVDLA with OpenCAPI so that the AI inference acceleration becomes possible with all components in open hardware community. The NVDLA RTL is modified and optimized for being integrated to OC-Accel framework, while the whole software stack of NVDLA is ported to OpenCAPI with kernel mode driver eliminated. The proposed NVDLA+OpenCAPI solution is able to run various deep neural networks such as AlexNet and YOLO for image classification and object detection with competitive performance speedup.

Speakers

Peng Fei Gou

Hardware Architect, IBM

Technical lead of IBM China OpenPOWER chip development team. Years of experience on state-of-the-art processor architecture research/development, industrial level CPU and SoC verification and compiler development. Works for projects such as IBM POWER9, OpenPOWER, OpenCAPI/CAPI, Nvidia... Read More →

NVDLA on OpenCAPI pdf

Thursday October 31, 2019 15:50 - 16:30 CET
Lumiere (Track 3)

OpenCAPI Machine Learning

Session Slides Included Yes

15:50 CET

Fedora CoreOS, Building and Running it for Power - Jakub Čajka, Red Hat, Inc.

Come to learn about Fedora CoreOS an automatically-updating, minimal Linux distribution for running containerized workloads securely and at scale. Its history, current status and future plans. How it is built in Fedora, challenges that were hit, and how you can run it on Power.

Speakers

Jakub Čajka

Software Engineer, Red Hat, Inc.

Software Engineer, currently working at Red Hat, Inc. in Fedora Multi-arch team enabling things for non-x86_64 architectures in Fedora project. In past worked at Red Hat as maintainer of Go compiler for RHEL.

Thursday October 31, 2019 15:50 - 16:30 CET
Tete d'Or AB (Track 1)

Software Development Cloud Linux OpenPOWER Ecosystem

15:50 CET

High-density OpenPOWER Dual-socket P9 System Design Example - Anton Smolenskiy, YADRO

Traditional mid-range storage systems use redundant servers as a storage controllers. Custom implementation of compute node at our YADRO’s modular storage system required new approach to the design process. During this presentation we will cover the whole design flow from drafting an idea to the final QA checks, touching unique lessons learned.

Speakers

Anton Smolenskiy

Hardware Lead, YADRO

Anton Smolenskiy is a Hardware Lead at YADRO. Anton is currently responsible for hardware design team operations. He is ivolved in design and bring-up of all YADRO server and storage products. Anton graduated Moscow State Technical University in 2006 and has more than 13 year expertise... Read More →

High density OpenPOWER Dual socket P9 System Design Example pdf

Thursday October 31, 2019 15:50 - 16:30 CET
Tete d'Or CD (Track 2)

Systems OpenPOWER Ecosystem

Session Slides Included Yes

16:40 CET

Counting the Stars, Neural Networks for Stars Classification - Emmanuel Foy, Atos

This talk describes the journey to counting stars in the milky way. It reports how Atos in collaboration with the European Space Agency experimented the AI neural network technology to process data from the Gaïa satellite.

Speakers

Emmanuel Foy

Escala Product Manager, Atos

Emmanuel is the Escala product manager at Atos. Escala is the product line for Power servers at Atos. Escala is an OEM of IBM who manufacture its Power server branded Atos in Europe and based in France.Emmanuel is also supporting the presales channels in configuring and sizing Escala... Read More →

Gaia Open Power Lyon October 2019LinuxFoundation pdf

Thursday October 31, 2019 16:40 - 17:10 CET
Tete d'Or AB (Track 1)

Machine Learning HPC OpenPOWER Ecosystem

Session Slides Included Yes

16:40 CET

High Bandwidth FPGA + GPU + Hardware Compression All-in-a-box - Alexandre Castellane & Bruno Mesnet, IBM France

Latest announcement concerning OpenPower foundation joining Linux Foundation and OpenCAPI reference designs being proposed lead to unprecedented opening of hardware to supercomputing open solutions.

We propose a simple example showing data acquisition and linearization in an FPGA followed by a processing of the data in a GPU and finally CPU hardware compression in the same server. The goal is to evaluate the different path contribution in terms of bandwidth on a typical computation server like the Power9 server AC922 using CAPI2, or even OpenCAPI very fast link, FPGA cards and V100 GPUs.

By adopting this all-in-a-box technology, you will free network resources, CPU usage, DDR usage, and have the most optimized dataflow for your data.

This example can find application in high density image acquisition and processing like photonic images in synchrotrons or medical X-ray images.

Speakers

Bruno Mesnet

CAPI/FPGA Accelerator enablement, IBM France

Alexandre Castellane

Senior Specialist Engineer, IBM France

OPF Lyon 31 09 2019 all in a box acquisition computing pdf

Thursday October 31, 2019 16:40 - 17:20 CET
Lumiere (Track 3)

FPGA GPU OpenCAPI

Session Slides Included Yes

17:30 CET

OpenPOWER Benefits in Data Processing & Analytics: Benchmark Comparison in a Large-scale Appliance PoC for a Customer - Nikolay Semenov, Yadro

YADRO will share comparative performance benchmarks obtained as a result of a large-scale PoC testing for a nation-wide retail network client. The client’s goal was to identify an optimal appliance solution for analyzing and segmenting its customers. During the test, YADRO OpenPOWER-based appliance was compared with the client’s current market-acclaimed database/analytics platform.

Speakers

Nikolay Semenov

Product Manager, Yadro

I am a product manager at YADRO responsible for server products. My product family is VESNIN and appliances made on this platform.

Thursday October 31, 2019 17:30 - 18:10 CET
Tete d'Or AB (Track 1)

Simulation OpenPOWER Ecosystem CPUs

17:30 CET

Tutorial Session Pre-Requisite: GPU Programming Using Patterns for Parallelization - Dr. Manuel Arenaz & Dr. Javier Novo, Appentra Solutions (Pre-registration Required; Limited Seating Available)

If you wish to participate in the Friday morning tutorial session hosted by Appentra, please plan to attend this preliminary session where you will receive any necessary assistance in getting the required tools installed, etc.

Please refer to the main session entry for details on what you will need to get the most from this session on Friday morning.

How to Register: Pre-registration is required for this session and to reserve your spot, please email appentra-tutorial-eu2019-info@openpowerfoundation.org. Seats are limited, and be sure to register right away.

The session leaders recommend downloading the Parallelware Trainer beforehand. A PDF document of the download instructions is attached.

Speakers

Dr. Manuel Arenaz

Arenaz, Appentra Solutions

Dr. Manuel Arenaz is the CEO of APPENTRA Solutions and professor at the University of A Coruña (Spain). He holds a PhD in Computer Science from the University of A Coruña (2003) on advanced compiler techniques for parallelisation of scientific codes. He is passionate about technology... Read More →

Dr. Javier Novo

Product Manager, Appentra Solutions

Dr. Javier Novo holds a PhD in Computer Science. He has more than 10 years of experience both in the academic world and in the private sector. He is currently Head of Engineering and Product at Appentra Solutions. He has extensive experience working with commercial customers in understanding... Read More →

Parallelware Trainer 1.3 Quick Installation Guide pdf

20191011 Parallelware Trainer Promotion Package pdf

0 Pre Requisite tutorial pdf

Thursday October 31, 2019 17:30 - 18:10 CET
Lumiere (Track 3)

Tutorial GPU HPC

Session Slides Included Yes

17:45 CET

All Attendee Reception & Sponsor Showcase

Thursday October 31, 2019 17:45 - 19:00 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

08:00 CET

Breakfast

Friday November 1, 2019 08:00 - 09:00 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

08:00 CET

Registration

Friday November 1, 2019 08:00 - 12:00 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

08:00 CET

Sponsor Showcase

Friday November 1, 2019 08:00 - 14:00 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

09:00 CET

Keynote: Welcome & Remarks - Hugh Blemings, OpenPOWER Foundation

Friday November 1, 2019 09:00 - 09:05 CET
Tete d'Or AB

Keynote Sessions

09:10 CET

Keynote: Zephyr Project, Open Hardware, Microwatt and OpenPOWER - Kate Stewart, Senior Director of Strategic Programs, The Linux Foundation

Hear the latest on the Zephyr™ Project, a scalable real-time operating system (RTOS) supporting multiple hardware architectures, optimized for resource-constrained devices, and built with safety and security in mind. You might even get to hear about the latest CPU architecture supported

Speakers

Kate Stewart

Senior Director of Strategic Programs, Linux Foundation

Kate Stewart is a Senior Director of Strategic Programs, responsible for Embedded and Open Compliance programs. Since joining The Linux Foundation, she has launched Real-Time Linux, Zephyr Project, CHAOSS, and ELISA.

Friday November 1, 2019 09:10 - 09:35 CET
Tete d'Or AB

Keynote Sessions

09:35 CET

Closing Remarks - Hugh Blemings, Executive Director, OpenPOWER Foundation

Friday November 1, 2019 09:35 - 09:40 CET
Tete d'Or AB

Keynote Sessions

09:40 CET

Morning Break

Friday November 1, 2019 09:40 - 09:55 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals

09:55 CET

Openpower as a backbone of Tvarit AI for its Industrial AI drive in Germany and How Customers are Responding to it - Hitesh Mittal, Tvarit

The foundation and driving factors for advancement of an AI is quality of data, availability of computing required for training, algorithmic Innovation and trust of the people. I will talk about the importance of these factors, Tvarit innovations related to these factors and how Openpower can play an important role in increasing the growth rate of the AI market. The main focus will be Industrial AI, Industry 4.0 and my experience with the German Market. Germany, is one of leader in Industry 4.0, is driving the growth of AI in Manufacturing and Automobile industry. I'll share customers biggest pain points when it comes to the adoption of advanced technologies such as HPCs and AI.

Speakers

Hitesh Mittal

Director - Business Development, Tvarit

Hitesh Mittal is electronics engineer, who also holds MBA degree from European Business School. He has worked with biggest automotive and energy companies like Continental Automotives and Reliance Industries Limited. He is AI enthusiast and currently working on the topics of Cognitive... Read More →

Friday November 1, 2019 09:55 - 10:35 CET
Tete d'Or AB (Track 1)

Machine Learning

09:55 CET

An introduction to CHIPS Alliance: Open Source IP and Tools for Collaborative Hardware Design - Michael Gielda, Antmicro

Speakers

Michael Gielda

Co-Founder, Antmicro

Michael Gielda is VP Business Development at Antmicro and chairs the Marketing Committees of Zephyr Project and CHIPS Alliance. A Computer Science graduate, he worked in IoT and embedded systems research before going on to found Antmicro, the open source technology and tools company... Read More →

Friday November 1, 2019 09:55 - 10:35 CET
Tete d'Or CD (Track 2)

Open Hardware

09:55 CET

Tutorial Session: GPU Programming Using Patterns for Parallelization - Dr. Manuel Arenaz & Dr. Javier Novo, Appentra Solutions (Pre-registration Required; Limited Seating Available)

As HPC continues to move towards a model of multicore and accelerator programming, a detailed understanding of shared-memory models and how best to use accelerators has never been more important. OpenMP is the de facto standard for writing multithreaded code to take advantage of shared memory platforms, but to make optimal use of it can be incredibly complex. OpenACC is considered a forerunner and simpler to use, which is why it is being successfully used today for the acceleration of real applications.

This course will give a holistic understanding of multicore and GPU programming using a novel productivity-oriented approach based on the decomposition of real applications into components for parallelization. The workshop will cover:
- Introduction to multicore and GPU programming.
- Code patterns for parallelization.
- OpenMP and OpenACC.
- Multithreading, offloading and tasking.

How to Register: Pre-registration is required for this session and to reserve your spot, please email appentra-tutorial-eu2019-info@openpowerfoundation.org. Seats are limited, and be sure to register right away.

Prerequisite: Please ensure you attend the pre-requisite session on Thursday afternoon at 17:30 in Lumiere (Track 3) to get the most out of this session. The session leaders recommend downloading the Parallelware Trainer beforehand. A PDF document of the download instructions is attached.

Speakers

Dr. Manuel Arenaz

Arenaz, Appentra Solutions

Dr. Javier Novo

Product Manager, Appentra Solutions

Parallelware Trainer 1.3 Quick Installation Guide pdf

20191011 Parallelware Trainer Promotion Package pdf

0 Pre Requisite tutorial pdf

0 Welcome pdf

1 Introduction pdf

2 Patterns pdf

4A Practicals PI LULESHmk pdf

OpenPOWER Summit Worksheet October pdf

Workshop Oct19 examples zip

Friday November 1, 2019 09:55 - 13:00 CET
Paul Bocuse - 2nd Floor

Tutorial GPU HPC

Session Slides Included Yes

10:45 CET

BoF Session: Microwatt FPGA CPU Core - Michael Neuling & Anton Blanchard, IBM

An opportunity to discuss the current state of the Microwatt FPGA Soft CPU Core implementation and ports

Speakers

Anton Blanchard

Distinguished Engineer, IBM

Michael Neuling

POWER Linux enablement, IBM

Friday November 1, 2019 10:45 - 11:25 CET
Tete d'Or AB (Track 1)

CPUs Open Hardware

10:45 CET

How to Run a MariaDB Clusters Over Multiple Arches - Toshaan Bharvani, VanTosh

This presentation will show how we run MariaDB Galera over ppc64le and x86_64, we run the instances on PowerEL which supports both architectures and has prepackaged MariaDB Galera so the deployment is easy and convenient, allowing the operator to focus on the exact MariaDB Galera setup and optimization. We even briefly show how to mix ppc64 and x86_64, just to prove we can do these type of setups.

Speakers

Thoshaan Bharvani

CTO, VanTosh

Toshaan Bharvani is a IT consultant, currently self-employed at VanTosh, with a interest in Open Source Software and Open Source Hardware. He started his IT interest at a very early age, when his father gave him his first own PC components. Ever since he has been interested in IT... Read More →

Friday November 1, 2019 10:45 - 11:25 CET
Tete d'Or CD (Track 2)

Databases

11:35 CET

BoF Session: OpenPOWER Hub Proposal - Jeff Scheel, IBM

Friday November 1, 2019 11:35 - 12:15 CET
Tete d'Or AB (Track 1)

OpenPOWER Ecosystem

11:35 CET

IBM Open: Power Ready Workgroup - Edmund Gamble, IBM

Provide an overview of what is required to get a hardware or software component certified as Open Power Ready. Describe the criteria required for certification, how this criteria is developed and modified by the Open Power Ready workgroup. Provide direction on how to participate in the Power Power Ready workgroup.

Speakers

Ned Gamble

IBM Senior Engineer, Open Power Chief Engineer and Chairman, Open Power Ready Workgroup, IBM

Ned is a Senior Engineer at IBM where he began there in the late 80s. He is currently the Open Power Chief Engineer and Chairman of the Open Power Ready Workgroup.

Friday November 1, 2019 11:35 - 12:15 CET
Tete d'Or CD (Track 2)

OpenPOWER Ecosystem

12:25 CET

Gender Identification of silkworm pupae Using Deep Learning with IBM OpenPOWER - Abhinandan S.P., The National Institute Of Engineering, Mysore

In the context of Industry 4.0, the development of process automation faces new challenges related to quality and efficiency. Silkworm sex identification is one of the most critical processes in the sericulture industry, if not done effectively, can hamper production. Our study aims at optimizing seed production of silkworms, which increases silk production by building a desired high accuracy model for silkworm gender identification. The model extracts general features and then classifies them under multiple labels based upon features detected.

Initially, we implemented Power AI Distributed Deep Learning (DDL) to train the datasets. Our state-of-the-art model achieves a test accuracy of 98.3%, higher than any existing models along with a reduction of around 75% training time compared to
a regular workstation.

Speakers

Abhinandan S.P.

Assistant Professor, The National Institute Of Engineering, Mysore

Friday November 1, 2019 12:25 - 13:05 CET
Tete d'Or AB (Track 1)

OpenPOWER Ecosystem

13:05 CET

Lunch (Provided for OpenPower Attendees)

Friday November 1, 2019 13:05 - 14:05 CET
Tete d'Or Foyer

Event Experience / Breaks / Meals